ams Breaks Ground on NY Wafer Fab

ams AG took a step forward in its long-term strategy of increasing manufacturing capacity for its high-performance sensors and sensor solution integrated circuits (ICs), holding a groundbreaking event at the site of its new wafer fabrication plant in Utica, New York.

ams sensor solutions are relied upon globally by manufacturers of smartphones, tablets and other communications devices, automakers, audio and medical equipment manufacturers and others. ams sensors are used in hundreds of millions of devices to recognize light, color, gestures, images, motion, position, environmental and medical parameters and more.

With construction work now underway on the new fab, ams remains on track to reach its target for the first batches of wafers made at the plant in the first half of 2018.

Production capacity at the Utica fab will supplement ams’ existing 180nm and 350nm CMOS and SiGe fab at its headquarters near Graz, Austria. Adding this additional volume to its in-house chip manufacturing facilities positions ams to meet the forecasted growth in demand for its high-performance sensor solution ICs.

New York Governor Andrew Cuomo has made public-private partnerships an important part of this Nano Utica initiative, which exceeds 4,000 projected jobs over the next decade. Designed to replicate the dramatic success of SUNY Poly’s Nanotech Megaplex in Albany, NANO Utica further cements New York’s international recognition as the preeminent hub for 21st century nanotechnology innovation, education, and economic development.

The new fab, which is being built to ams’ specifications and which ams will operate under a 20-year lease, is expected initially to offer capacity of at least 150,000 200mm-wafer equivalents per year. Planned expansion thereafter will eventually see the plant operating at a capacity of more than 450,000 200mm-wafer equivalents per year.

The new fab is located close to a campus of SUNY Polytechnic Institute in New York’s Tech Valley, the largest region focused on technology manufacturing in the US and home to other nanotechnology and semiconductor companies. The fab will be capable of producing wafers at the 130nm node, and more advanced nodes in the future.

The new fab site also marked the success of the partnership behind the project to build, equip and operate another high-technology manufacturing facility in the State of New York. This partnership has benefited from a wide-ranging collaboration between public sector bodies such as the New York governor’s office, the City of Utica and the State University of New York, and various private sector institutions including ams, the fab’s sole leaseholder.

“Building this new wafer fab enables ams to achieve its plans for growth and to meet the increasing demand for sensor solutions produced at advanced manufacturing nodes. Our decision to locate the facility in New York was motivated by the availability of a highly skilled workforce, the proximity to prestigious educational and research institutions, and the favorable business environment, backed by public and private partners,” CEO Alexander Everke said. “What we will create together in Utica will be the most productive ‘More than Moore’ fab worldwide,” he added.

India Wafer Fab Project in Jeopardy

For years now, the Indian government has been set on building two wafer fabs in the sub-continent but latest developments show that the project is being put on hold, at least on one front.

Local reports say that Jaiprakash Associates, Local cement and infrastructure company, also the top partner in a consortium with IBM and Tower Semiconductor Ltd. withdrew from its project to build a wafer fab in Greater Noida in Uttar Pradesh.

"JP Associates has withdrawn its proposal of semiconductor plant. They have said that it is not commercially viable to set up this plant at present," Aruna Sharma, secretary of the DeitY (Department of Electronics and IT) of the ministry of communications & information technology, government of India told reporters on the sidelines of a Qualcomm event in New Delhi.

Estimates of spending on the fab vary from Rs.27,027.03 crore (about $4 billion) up to Rs.33,783.78 crore (about $5 billion) but are somewhat moot as the premise of the projects was that the government would provide funding to subsidize the consortium's plans. Jaypakash Associates was reported to have high levels of indebtedness.

A spokesperson for Tower Semiconductor Ltd. (Migdal Haemek, Israel) confirmed JP's withdrawal in an email response to EE Times Europe.

"Indeed JP has withdrawn their part of our consortium. They had the role of investing money in this project. At this point, we are looking for other investors who may have interest in joining this deal," the spokesperson said. "Nevertheless, [you] need to remember that this deal was never part of our business plan, nor in any of our analysts' models."

The slowness of the Indian government, its lack of ability to raise funds, seem to have blighted both wafer fabs.

Jaiprakash Associates and Hindustan Semiconductor Manufacturing Co. (HSMC) were the two consortia approved by government of India to construct wafer fabs back in 2012. The Indian government's thinking was that its negative balance of trade in chips needed to be addressed and it was not sufficient to only try and compensate for that in electronic systems-level activity and software writing.

According to the local reports the JP wafer fab was expected to cost about Rs.27,027.03 crore ($4 billion) in total and be capable of running 300mm-diameter wafers and run 40,000 wafer starts per month in an advanced CMOS. The plan was to have Tower run the wafer fab as a whole and for IBM to provide CMOS manufacturing processes. The fab would start on 90, 65 and 45nm CMOS nodes before moving on to 28nm CMOS and a 22nm node, still behind today's leading edge in chip manufacturing, but potentially useful for applications in the Internet of Things.

Meanwhile the Hindustan Semiconductor Manufacturing Co. (HSMC), which is linked to STMicroelectronics and Silterra, Malaysia is still expected to move from 90nm down to 28nm and 20nm at a proposed location in Prantij, near Gandhinagar, Gujarat at cost of about Rs.25,675.68 crore (about $3.8 billion).

However, the HSMC project has received the boost of reported support from Lisu Su, CEO of Advanced Micro Devices Inc. Local reports said that Su had met with Ravi Shankar Prasad, Indian telecom minister, and discussed matters linked to semiconductor policy and its HMSC fab proposal. According to the reports, AMD wants to help transform India into an electronics manufacturing hub.

A third plan to foster a wafer fab in India comes from Cricket Semiconductor LLC, which wants to create an analogue and power pure-play foundry near Indore in Madhya Pradesh. This plan came to light in 2015 but still requires details on funding, technology and customers.

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