SEMICONDUCTOR INDUSTRY
UPDATE
April 2016
McIlvaine Company
TABLE OF
CONTENTS
Imec 300mm Cleanroom, Leuven, Belgium
Monocrystal Expanding Capacity
Renesas Transfers Wafer Fab to TDK
Alpha and Omega Semiconductor forms Joint Venture
Agreement in China
TSMC Plans First 300mm Wafer Fab in China
Cost: €1 billion (US$1,116,750,000)
Size: 43,040 sq. ft. (4,000 sq. m.)
Description: Imec’s new 300mm cleanroom is one of the most
advanced research facilities in the world dedicated to scaling IC technology
beyond 7nm. Its addition now brings imec’s total semiconductor research
cleanrooms to 129,120 sq. ft. (12,000 sq. m.). The facility will be able to
serve the entire semiconductor ecosystem, complies with the newest standards in
the semiconductor industry, and provides additional space for the most advanced
tools that will lead innovations in new device and system concepts.
The cleanroom includes a “waffle table’,” a 3-ft. thick
concrete slab that forms the basis of the cleanroom. Its structure rests on 831
concrete piles placed 60 feet deep in the ground, making it totally
vibration-free and ensuring precision accuracy down to a millionth of a
millimeter. The waffle table lies 50 feet above ground and is perforated with no
less than 3,300 holes (400 mm diameter), and there is constant air circulation.
To further drive Moore’s Law, crucial innovations are required
and imec offers the ideal environment for cost and time effective semiconductor
R&D advanced on materials, process steps, modules and novel device concepts for
CMOS technologies at least two generations ahead of manufacturing. Imec’s
fundamental understanding and ability to bridge the gap between theory and
practice will define the new innovations this cleanroom will generate.
Imec’s partners—which includes foundries, IDMs, fabless and
fablite companies, equipment and material suppliers—will benefit from the
equipment to develop innovative solutions for more powerful, high-performing,
cheaper and energy-efficient ICs which are crucial in the evolution of a
sustainable digital future. The cleanroom complements imec’s other production
facilities including its bio-nanolabs, neuroelectronics labs, imaging and
wireless and electronics test labs, photovoltaic pilot lines, and GaN-on-Si,
Silicon photonics and MEMS pilot lines.
The cleanroom was constructed by M+W, an internationally
renowned contractor of large-scale high-tech infrastructure. The architecture
was designed by Stéphane Beel and includes a reflecting façade which is intended
to integrate the building with the environment. Responsible for imec’s campus
buildings is Wim Mertens.
The one billion Euro cost comprises both the building and
equipment. imec received 100 million euro in funding from the Flemish government
and more than 900 million euro in investments from joint R&D partners within the
semiconductor industry.
Completion date: The cleanroom opened on March 10, 2016.
Installations of the first tools began in January 2016—the project lasted a
total of 20 months.
Russia-based sapphire maker Monocrystal has expanded monthly
production capacity from four million mm in 2015 to 4.5 million mm currently,
and aim to reach five million mm by the end of 2016, according to Monocrystal
Taiwan.
Monocrystal's capacity expansion aims to increase its global
market share, Monocrystal Taiwan said. Through the capacity expansion,
Monocrystal's global market share will rise from 25-30% in 2015 to over 30% in
2016.
Of Monocrystal-produced sapphire, 60% is used to make LED
epitaxial wafers and 30% for optical applications.
Due to a global oversupply, prices for 2-inch sapphire ingots
have drastically dropped from the highest level of US$25/mm to below US$2/mm,
driving many makers out of the market, Monocrystal Taiwan noted. While 4-inch
has become a mainstream size for sapphire wafers used by LED epitaxial wafer
makers, prices for 4-inch sapphire ingots fell from US$10-12/mm to US$8/mm in
2015. Wafer prices are expected to further drop by less than 20% in 2016,
Monocrystal Taiwan indicated.
TDK Corp., Renesas Electronics Corp. and Renesas Semiconductor
Manufacturing Co. Ltd have entered a deal on November 27, 2015 under which
Renesas Semiconductor Manufacturing's Tsuruoka Factory will be transferred to
TDK. The three companies target to conclude a definitive agreement on the
transfer by the end of February 2016, and are now negotiating the details,
including the handover date and the transfer (reemployment) of personnel
employed at the Tsuruoka Factory.
In the news release "Renesas Electronics Shows Direction of
Renesas Group," announced on August 2, 2013, Renesas Electronics indicated its
intentions for the Tsuruoka Factory (then the 5in front-end wafer fabrication
line of Renesas Yamagata Semiconductor Co. Ltd's Tsuruoka Higashi Factory) as
"planned to be closed in two or three years," and plans were proceeding to close
the factory by the end of the current fiscal year.
TDK, for its part, has identified the electronic components
business based on magnetic materials technology as a core business. It considers
its three priority markets to be the ICT market, which encompasses products such
as smartphones that continue to be increasingly popular worldwide; the
automotive market, which includes hybrid vehicles and electric vehicles; and the
industrial equipment/energy market, which covers applications such as wind power
generation and solar power generation.
TDK is intensely focused on efforts to expand these businesses
and their profitability through a concentration on the electronic components
business targeted at these three markets. To assure future growth, TDK is
working to take thin-film technology built up over many years for the
manufacture of magnetic heads for hard disk drives and extend it laterally into
electronic components. In order to respond in a timely manner to the vigorous
demand of thin-film components that demonstrate the company's strengths
centering the three priority markets, TDK decided to acquire Renesas
Semiconductor Manufacturing's Tsuruoka Factory.
TDK approached Renesas and Renesas Semiconductor Manufacturing
in early October of this year with a view toward acquiring the Tsuruoka Factory.
The three parties were able to come to a meeting of minds, and as a result, a
basic agreement regarding transfer of the Tsuruoka Factory was concluded.
Negotiations on detailed conditions will continue with the aim of concluding a
definitive agreement at a future date.
Toshiba this month has announced plans to build a new
manufacturing facility to produce its BiCS NAND flash memory. The company
intends to start making chips at the new fab in 2018 and currently is not
disclosing the planned production capacity of the factory. SanDisk yet has to
confirm its participation in building the new fab, but the announcement itself
means that despite an ongoing financial scandal, Toshiba is set to remain one
the world’s largest makers of NAND flash memory.
Toshiba plans to invest around ¥360 billion ($3.233 billion)
in its new facility in fiscal 2016 to fiscal 2018, with that price tag covering
both construction costs and equipment investments. The fab will be located on
land adjacent to the Yokkaichi Operations memory production complex in Mie
prefecture, which means that the company essentially wants to add a new
production complex to its Fab 5 (which is currently produces 2D NAND) and Fab 2.
Exact decisions regarding construction schedule, manufacturing tools and other
will be made in Toshiba’s fiscal 2016, which begins in April.
Construction of a semiconductor manufacturing facility usually
takes about a year. After the building is complete inside and outside, it takes
about two or three quarters to move in equipment and start volume production.
Therefore, Toshiba’s plan to begin operating the new facility in fiscal 2018
(which begins on April 1, 2018) seems viable.
The new fab will solely produce Toshiba’s 3D NAND memory,
which the company calls BiCS (Bit Cost Scalable) NAND. Toshiba claims that the
architecture of its proprietary BiCS NAND is more efficient in terms of die
sizes compared to other types of 3D NAND thanks to its U-shaped NAND string. So
far independent analysts have not verified whether Toshiba’s 48-layer 256 Gb TLC
BiCS NAND chips are smaller or larger than Samsung’s 48-layer 256 Gb TLC V-NAND
ICs, but if this proves to be the case, then Toshiba will enjoy lower production
costs over time.
Meanwhile at present, Toshiba and SanDisk already operate
multiple fabs for non-volitile memory, including the world’s largest NAND flash
manufacturing facility, Fab 5 (phases 1 and 2) at the Yokkaichi Operations
memory production complex in Mie Prefecture. Ahead of their newly announced fab
for 2018, Toshiba and SanDisk are scheduled to produce their BiCS NAND memory at
both Fab2 and Fab 5 over the next year. BiCS production at Fab 2 is set for the
first half of FY2016 (i.e., from April to October, 2016), and SanDisk has
previously indicated that it would begin conversion of some of the capacity in
Fab 5 to 3D NAND in 2016. Keeping in mind that SanDisk cannot do anything in the
fab alone, it is clear that Toshiba and SanDisk have a plan to gradually convert
the fab to 3D NAND in the future.
If Toshiba’s plan succeeds, by the second half of calendar
2018 it will have several semiconductor manufacturing facilities capable of
producing BiCS NAND memory. While the combined manufacturing capacities of all
three fabs are unknown at the moment, it is likely that the company will
continue to produce vast amounts of NAND flash memory.
Toshiba said that it expected to continue its joint venture
operation with SanDisk in expanding BiCS Flash capacity in the new facility.
However, SanDisk is being acquired by Western Digital at the moment and it
remains to be seen on what terms the new company will join Toshiba in
investments.
Together, Toshiba and SanDisk currently make and sell more
flash memory than Samsung, but keeping in mind how aggressively the latter plans
to expand its semiconductor manufacturing capacities in the coming years,
everything is subject to change. Last year Samsung announced plans to invest an
additional $9.2 billion in expansion of its manufacturing facility near
Pyeongtaek, South Korea. The latter will cost Samsung $14.4 billion and is
scheduled to begin operations in 2017. While the fab is officially intended for
DRAM production, its vast manufacturing capacities could be used to produce
other types of semiconductors as well.
Alpha and Omega Semiconductor Limited, a designer, developer
and global supplier of a broad range of power semiconductors and power ICs,
announced that it has executed a definitive agreement with two strategic
investment funds owned by the Municipality of Chongqing, China, to form the
previously announced joint venture for a new state-of-the-art power
semiconductor packaging/testing and wafer fabrication facility in the Liangjiang
New Area of Chongqing.
The initial capitalization of the Joint Venture under the
agreement will be $330 million. This reflects cash contributions, primarily from
the Chongqing funds, as well as existing packaging and testing equipment from
AOS, and certain AOS intellectual property relating to packaging and wafer
manufacturing technology. AOS will own 51%, and the Chongqing funds will own
49%, of the equity interest in the Joint Venture.
The Joint Venture agreement is subject to approval by the relevant
Chinese authorities.
"We are excited to begin this partnership, which we believe
will enable both AOS and Chongqing to grow and prosper," said Dr. Mike Chang,
chairman and CEO of AOS. "This
joint venture with Chongqing represents an important milestone in our strategic
roadmap. It will help further diversify our offerings of power semiconductor
products and improve our access to customers in China as we work to accelerate
our long-term growth and profitability."
The Joint Venture is expected to commence its initial
packaging production in mid 2017.
Prior to that, AOS intends to gradually relocate a majority of its assembly and
testing equipment to the Joint Venture from its existing facility in Shanghai,
which will continue as a center of supply chain management, technology
development, and high-value production.
Over the longer term, the Joint Venture expects to construct a 12-inch
wafer fabrication facility for the production of power semiconductors.
The Joint Venture is designed to bring together the
technological and operational capability of AOS in power semiconductor product
manufacturing with the capital resources and regional infrastructure support of
the Chongqing authority.
After
disclosing plans to set up a $3 billion fab investment in China last December,
Taiwan Semiconductor Manufacturing Co. (TSMC), has announced that it has signed
an agreement with the Nanjing municipal government for the facility.
TSMC
(Nanjing) Co. Ltd., a wholly owned subsidiary of TSMC managing a 12-inch
wafer fab
and a design service centre, will be located in the Pukou Economic Development
Zone. Planned capacity is 20,000 12in wafers per month, and the facility is
expected to ramp up TSMC's 16nm process in the Nanjing fab during the second
half of 2018.
"With our
12-inch fab and our design service centre in Nanjing, we aim to provide closer
support to customers as well as expand our business opportunities in China in
step with the rapid growth of the Chinese semiconductor market over the last
several years," said TSMC Chairman Morris Chang.
The company
began commercial production of 16nm process technology in 2015, when it
accounted for more than half of the global foundry market for 14/16nm products,
according to TSMC. The company forecasts significant increases in its 14-16nm
market share for 2016.
TSMC said it
has more than 100 customers in China. It is joining a growing list of chipmakers
that have already started 12-inch fab projects in China, which, according to
industry organization Semiconductor Equipment and Materials International
(SEMI), has one of the world's largest semiconductor markets, yet imports most
of the chips it uses to assemble products, such as Apple iPads and iPhones.
TSMC would
join Intel, Samsung, SK Hynix and Chinese chipmakers such as Semiconductor
Manufacturing International Corp. (SMIC), which have opened or are underway with
projects to make chips on 12-inch wafers, according to SEMI.
TSMC's
compound annual growth rate for revenue from Chinese customers, including chip
design companies such as HiSilicon, has exceeded 50% in the past five years.
TSMC expects
the fab headcount to be 1,200. Initially, staff from Taiwan and an existing
8-inch fab located in Shanghai will help with construction and the production
ramp up at Nanjing, with additional local hiring as the schedule proceeds.
Before volume production starts, staff transferred from Taiwan will account for
more than 50% of the personnel at Nanjing.
The Taiwan
government has restricted domestic chip investments in China on concerns it will
lose jobs and technology.
TSMC said it
will keep its most advanced process technologies, key production lines, and core
R&D efforts in Taiwan. The investment in China is aimed at increasing business
opportunities in China, which TSMC said will have a positive effect on
additional expansion in Taiwan.
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