SEMICONDUCTOR INDUSTRY UPDATE
July 2014
McIlvaine Company
TABLE OF
CONTENTS
CNE
Cleanroom Certified in Russia’s First 300mm Fab
Everlight
to Expand Monthly LED Packaging Capacity
State
Building Semiconductor Lab in New York
GE to
Lead Electronics Manufacturing Consortium
IBM
Invests $3 Billion in Chip and Semiconductor Research
Memsstar
relocates to Class 1,000 Facility
Crocus Nano Electronics (CNE), the joint venture founded in 2011 by Crocus Technology, a developer of magnetically enhanced semiconductor technologies and Rusano, a Russian state-owned investment company are focused on developing the Russian nanotechnology industry.
They have successfully passed certification of the cleanroom in Moscow according to ISO 14644-1 requirements.
The cleanroom is certified as Class 1,000 (ISO 6) in the production area. The cleanroom is ready for equipment installation and forms the heart of the first 300mm wafer fab in Russia, which will be capable of processing up to 1,000 wafers per week.
“Our cleanroom certification is a very important milestone in the preparation of our fab. Equipment hook-up is expected to occur in the next quarter and we expect to begin process qualification of our fab equipment in September 2014. The achievement of this milestone is also attributed to our general contractor, Faeth, who completed the facilities and cleanroom works and has been awarded the hook-up contract as well,” says Mark Dydyk, CEO of CNE.
Everlight Electronics started expanding its LED packaging capacity in June and when the expansion completes in September, its monthly capacity will have increased by 500 million LED chips to reach four billion units in total, according to company chairman Robert Yeh.
The expansion focuses on packaging LED chips mainly for TV backlighting and general lighting applications, Yeh indicated. Currently TV backlighting and lighting account for 20% and 12.5%, respectively, of Everlight's consolidated revenues.
Through partnership with LED epitaxial wafer and chip maker Epistar, Everlight aims to surpass Japan-based Nichia to become the world's largest LED packager in two years, Yeh said.
The state is building a next-generation semiconductor facility in Greece that'll be shared by approximately 100 tech companies. Officials say the facility should create at least 500 jobs in Rochester.
The facility will be located at the SUNY College of Nanoscale Science and Engineering Rochester Facility building in the Canal Landing Office Park in Greece. The state and college are constructing clean rooms in the building, which will also house a previously announced solar cell research facility.
Kaloyeros said the project is the second part of the New York Power Electronics Manufacturing Consortium, which state officials announced at a General Electric facility in Niskayuna in Schenectady County. The idea is to advance the development and manufacturing of next-generation computer chips in New York, he said.
The consortium entails a $500-million investment in state-owned semiconductor research and development facilities, which the companies will be able to use. The state government is putting up $135 million of that funding, Cuomo said, and the rest is coming from private investment
The Rochester facility will focus on gallium nitride semiconductor technology, Cuomo said. And Kaloyeros said that the facility will include a 200 millimeter wafer fabrication line. The state will partner with the tech companies via SEMATECH, a semiconductor industry umbrella association, which is moving from Texas to New York. Its members include General Electric, IBM, Global Foundries, Samsung, and Intel.
"This is really the future of computer technology," Kaloyeros said.
At the GE Global Research Center in Niskayuna, NY, Governor Andrew M. Cuomo has announced that New York State will partner with over 100 private companies, led by General Electric (GE) and including GlobalFoundries, Lockheed Martin and IBM, to launch the New York Power Electronics Manufacturing Consortium (NY-PEMC). The public-private partnership will invest more than $500m over five years, focused on the development of next-generation wide-bandgap semiconductor materials and processes at the State-owned R&D facility in Albany, NY.
“This partnership will create thousands of new jobs in Upstate New York [including at least 500 in the Capital region], tapping into our highly trained workforce and existing centers of high-tech research and development,” says Cuomo.
Managed through the newly merged State University of New York (SUNY) College of Nanoscale Science and Engineering (CNSE)/SUNY Institute of Technology (SUNYIT), wide-bandgap semiconductors enable power devices to get smaller, faster and more efficient as silicon reaches its limits. “Power electronics is one of the fastest-growing global markets,” comments SUNY CNSE/SUNYIT’s CEO & officer in charge Dr Alain Kaloyeros
The Albany site will act as a global ‘open-innovation’ user-shared facility, enabling the expansion and growth of corporate partners as well as small- and medium-sized enterprises (SMEs).
NY-PEMC places New York at the forefront of the next revolution in power, believes GE’s chairman & CEO Jeff Immelt. “By partnering, we are bringing breakthrough reliable technology to market faster and at lower cost so our customers and global industries see major productivity gains and operate at peak efficiency.”
GE will be a lead partner in the fab, housed at the CNSE Nano Tech complex, which aims to develop and produce low-cost 6” silicon carbide (SiC) wafers. The advantages of SiC-based power electronic devices over silicon include the capacity to handle much higher frequencies and temperatures, reducing the size and cost for companion filtering and cooling systems. Also, the devices can be half the size of similar silicon devices, providing increased power density and reliability. Currently, SiC technology can be cost prohibitive to smaller- to medium-size companies. All NY-PEMC partner companies will have access to 6” SiC tools and a baseline process flow, contributed by GE, where they can make their own enhancements in preparation for high-volume, cost-effective manufacturing.
The partnership is enabled by the START-UP NY tax-free initiative, in addition to $135m in New York State funds provided to CNSE for the establishment of the NY-PEMC facilities, which will attract $365m in private funds and know-how (including more than $100m from GE) to support personnel, equipment and process flow, tool installation, facilities and materials, making a total 5-year investment of $500m. Collaboration with CNSE should enable the expansion and growth of both major corporate partners and small- and medium-sized enterprises within a power electronics device and systems integration eco-system.
IBM has announced it is investing $3 billion over the next
five years in two broad research and early stage development programs to push
the limits of chip technology needed to meet the emerging demands of cloud
computing and Big Data systems. These investments will push IBM's semiconductor
innovations from today’s breakthroughs into the advanced technology leadership
required for the future.
The first research program is aimed at so-called “7
nanometer and beyond” silicon technology that will address serious physical
challenges that are threatening current semiconductor scaling techniques and
will impede the ability to manufacture such chips. The second is focused on
developing alternative technologies for post-silicon era chips using entirely
different approaches, which IBM scientists and other experts say are required
because of the physical limitations of silicon based semiconductors.
Cloud and big data applications are placing new challenges
on systems, just as the underlying chip technology is facing numerous
significant physical scaling limits.
Bandwidth to memory, high speed communication and device power
consumption are becoming increasingly challenging and critical.
The teams will comprise IBM Research scientists and
engineers from Albany and Yorktown, N.Y.; Almaden, Calif.; and Europe. In
particular, IBM will be investing significantly in emerging areas of research
that are already underway at IBM such as carbon nanoelectronics, silicon
photonics, new memory technologies, and architectures that support quantum and
cognitive computing.
These teams will focus on providing orders of magnitude
improvement in system level performance and energy efficient computing. In
addition, IBM will continue to invest in the nanosciences and quantum
computing--two areas of fundamental science where IBM has remained a pioneer for
over three decades.
IBM Researchers and other semiconductor experts predict
that while challenging, semiconductors show promise to scale from today's 22
nanometers down to 14 and then 10 nanometers in the next several years.
However, scaling to 7 nanometers and perhaps below, by the end of the
decade will require significant investment and innovation in semiconductor
architectures as well as invention of new tools and techniques for
manufacturing.
"The question is not if we will introduce 7 nanometer
technology into manufacturing, but rather how, when, and at what cost?" says
John Kelly, senior vice president, IBM Research. "IBM engineers and scientists,
along with our partners, are well suited for this challenge and are already
working on the materials science and device engineering required to meet the
demands of the emerging system requirements for cloud, big data, and cognitive
systems. This new investment will ensure that we produce the necessary
innovations to meet these challenges."
"Scaling to 7nm and below is a terrific challenge, calling
for deep physics competencies in processing nano materials affinities and
characteristics. IBM is one of a very few companies who has repeatedly
demonstrated this level of science and engineering expertise," says Richard
Doherty, technology research director, The Envisioneering Group.
Silicon transistors, tiny switches that carry information
on a chip, have been made smaller year after year, but they are approaching a
point of physical limitation. Their increasingly small dimensions, now reaching
the nanoscale, will prohibit any gains in performance due to the nature of
silicon and the laws of physics. Within a few more generations, classical
scaling and shrinkage will no longer yield the sizable benefits of lower power,
lower cost and higher speed processors that the industry has become accustomed
to.
With virtually all electronic equipment today built on
complementary metal–oxide–semiconductor (CMOS) technology, there is an urgent
need for new materials and circuit architecture designs compatible with this
engineering process as the technology industry nears physical scalability limits
of the silicon transistor.
Beyond 7 nanometers, the challenges dramatically increase,
requiring a new kind of material to power systems of the future, and new
computing platforms to solve problems that are unsolvable or difficult to solve
today. Potential alternatives include new materials such as carbon nanotubes,
and non-traditional computational approaches such as neuromorphic computing,
cognitive computing, machine learning techniques, and the science behind quantum
computing.
As the leader in advanced schemes that point beyond
traditional silicon-based computing, IBM holds over 500 patents for technologies
that will drive advancements at 7nm and beyond silicon -- more than twice the
nearest competitor. These continued investments will accelerate the invention
and introduction into product development for IBM's highly differentiated
computing systems for cloud, and big data analytics.
Several exploratory research breakthroughs that could lead
to major advancements in delivering dramatically smaller, faster and more
powerful computer chips, include quantum computing, neurosynaptic computing,
silicon photonics, carbon nanotubes, III-V technologies, low power transistors
and graphene:
The most basic piece of information that a typical computer
understands is a bit. Much like a light that can be switched on or off, a bit
can have only one of two values: "1" or "0.” Described as superposition, this
special property of qubits enables quantum computers to weed through millions of
solutions all at once, while desktop PCs would have to consider them one at a
time.
IBM is a world leader in superconducting qubit-based
quantum computing science and is a pioneer in the field of experimental and
theoretical quantum information, fields that are still in the category of
fundamental science - but one that, in the long term, may allow the solution of
problems that are today either impossible or impractical to solve using
conventional machines. The team recently demonstrated the first experimental
realization of parity check with three superconducting qubits, an essential
building block for one type of quantum computer.
Bringing together nanoscience, neuroscience, and
supercomputing, IBM and university partners have developed an end-to-end
ecosystem including a novel non-von Neumann architecture, a new programming
language, as well as applications. This novel technology allows for computing
systems that emulate the brain's computing efficiency, size and power usage.
IBM’s long-term goal is to build a neurosynaptic system with ten billion neurons
and a hundred trillion synapses, all while consuming only one kilowatt of power
and occupying less than two liters of volume.
IBM has been a pioneer in the area of CMOS integrated
silicon photonics for over 12 years, a technology that integrates functions for
optical communications on a silicon chip, and the IBM team has recently designed
and fabricated the world's first monolithic silicon photonics based transceiver
with wavelength division multiplexing.
Such transceivers will use light to transmit data between different
components in a computing system at high data rates, low cost, and in an
energetically efficient manner.
Silicon nanophotonics takes advantage of pulses of light
for communication rather than traditional copper wiring and provides a super
highway for large volumes of data to move at rapid speeds between computer chips
in servers, large datacenters, and supercomputers, thus alleviating the
limitations of congested data traffic and high-cost traditional interconnects.
Businesses are entering a new era of computing that
requires systems to process and analyze, in real-time, huge volumes of
information known as Big Data. Silicon nanophotonics technology provides answers
to Big Data challenges by seamlessly connecting various parts of large systems,
whether few centimeters or few kilometers apart from each other, and move
terabytes of data via pulses of light through optical fibers.
IBM researchers have demonstrated the world’s highest
transconductance on a self-aligned III-V channel metal-oxide semiconductor (MOS)
field-effect transistors (FETs) device structure that is compatible with CMOS
scaling. These materials and structural innovation are expected to pave path for
technology scaling at 7nm and beyond.
With more than an order of magnitude higher electron mobility than
silicon, integrating III-V materials into CMOS enables higher performance at
lower power density, allowing for an extension to power/performance scaling to
meet the demands of cloud computing and big data systems.
IBM Researchers are working in the area of carbon nanotube
(CNT) electronics and exploring whether CNTs can replace silicon beyond the 7 nm
node. As part of its activities for
developing carbon nanotube based CMOS VLSI circuits, IBM recently demonstrated
-- for the first time in the world -- 2-way CMOS NAND gates using 50 nm gate
length carbon nanotube transistors.
IBM also has demonstrated the capability for purifying
carbon nanotubes to 99.99 percent, the highest (verified) purities demonstrated
to date, and transistors at 10 nm channel length that show no degradation due to
scaling--this is unmatched by any other material system to date.
Carbon nanotubes are single atomic sheets of carbon rolled
up into a tube. The carbon nanotubes form the core of a transistor device that
will work in a fashion similar to the current silicon transistor, but will be
better performing. They could be used to replace the transistors in chips that
power data-crunching servers, high performing computers and ultra fast smart
phones.
Carbon nanotube transistors can operate as excellent
switches at molecular dimensions of less than ten nanometers – the equivalent to
10,000 times thinner than a strand of human hair and less than half the size of
the leading silicon technology. Comprehensive modeling of the electronic
circuits suggests that about a five to ten times improvement in performance
compared to silicon circuits is possible.
Graphene is pure carbon in the form of a one atomic layer
thick sheet. It is an excellent
conductor of heat and electricity, and it is also remarkably strong and
flexible. Electrons can move in
graphene about ten times faster than in commonly used semiconductor materials
such as silicon and silicon germanium. Its characteristics offer the possibility
to build faster switching transistors than are possible with conventional
semiconductors, particularly for applications in the handheld wireless
communications business where it will be a more efficient switch than those
currently used.
Recently in 2013, IBM demonstrated the world's first
graphene based integrated circuit receiver front end for wireless
communications. The circuit consisted of a 2-stage amplifier and a down
converter operating at 4.3 GHz.
In addition to new materials like CNTs, new architectures
and innovative device concepts are required to boost future system performance.
Power dissipation is a fundamental challenge for nanoelectronic circuits. To
explain the challenge, consider a leaky water faucet -- even after closing the
valve as far as possible water continues to drip -- this is similar to today’s
transistor, in that energy is constantly "leaking" or being lost or wasted in
the off-state.
A potential alternative to today’s power hungry silicon
field effect transistors are so-called steep slope devices. They could operate
at much lower voltage and thus dissipate significantly less power. IBM
scientists are researching tunnel field effect transistors (TFETs). In this
special type of transistors the quantum-mechanical effect of band-to-band
tunneling is used to drive the current flow through the transistor. TFETs could
achieve a 100-fold power reduction over complementary CMOS transistors, so
integrating TFETs with CMOS technology could improve low-power integrated
circuits.
Recently, IBM has developed a novel method to integrate
III-V nanowires and heterostructures directly on standard silicon substrates and
built the first ever InAs/Si tunnel diodes and TFETs using InAs as source and Si
as channel with wrap-around gate as steep slope device for low power consumption
applications.
"In the next ten years computing hardware systems will be
fundamentally different as our scientists and engineers push the limits of
semiconductor innovations to explore the post-silicon future," says Tom
Rosamilia, senior vice president, IBM Systems and Technology Group. "IBM
Research and Development teams are creating breakthrough innovations that will
fuel the next era of computing systems."
IBM's historic contributions to silicon and semiconductor
innovation include the invention and/or first implementation of: the single cell
DRAM, the “Dennard scaling laws” underpinning "Moore's Law", chemically
amplified photoresists, copper interconnect wiring, Silicon on Insulator,
strained engineering, multi core microprocessors, immersion lithography, high
speed silicon germanium (SiGe), High-k gate dielectrics, embedded DRAM, 3D chip
stacking, and Air gap insulators.
IBM researchers also are credited with initiating the era
of nano devices following the Nobel prize winning invention of the scanning
tunneling microscope which enabled nano and atomic scale invention and
innovation.
IBM will also continue to fund and collaborate with
university researchers to explore and develop the future technologies for the
semiconductor industry. In particular, IBM will continue to support and fund
university research through private-public partnerships such as the
NanoElectornics Research Initiative (NRI), and the Semiconductor Advanced
Research Network (STARnet), and the Global Research Consortium (GRC) of the
Semiconductor Research Corporation.
Memsstar Ltd., a provider of etch and deposition equipment
and technology solutions to manufacturers of semiconductors and micro-electrical
mechanical systems (MEMS), has relocated to a new, larger facility.
“This move positions Memsstar extremely well to support the
rapidly growing European semiconductor and global MEMS markets,” says Tony McKie,
CEO. “Our strong background in semiconductor etch and deposition processes
positions us to deliver the most advanced MEMS platforms and best remanufactured
equipment in the industry. With strong growth on the horizon, investing in our
facilities and infrastructure ensures that we can continue to meet customer
demand.”
Located in Livingston, Scotland, the 5,200 ft2 facility houses the company’s corporate headquarters, manufacturing, spare parts, and customer training facilities. The facility has a state-of-the-art 980 ft2 Class 1,000 cleanroom for manufacturing in addition to dedicated clean facilities and service areas. Representing a 40% increase in manufacturing capacity over the company’s prior location, cleanroom space will be dedicated to manufacturing Memsstar’s MEMS platforms for the global marketplace and remanufacturing etch and deposition equipment from Lam, Novellus, and Applied Materials to serve its European semiconductor customers.
McIlvaine Company
Northfield, IL 60093-2743
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