SMIC and JCET Establish a Joint Venture in Jiangyin

Semiconductor Manufacturing International Corporation the largest and most advanced pure foundry provider in China; and Jiangsu Changjiang Electronics Technology Co., Ltd., the largest packaging service provider in China, jointly announced the formation of a joint venture for 12-inch bumping and related testing, from the previously signed joint venture agreement, which will be established in Jiangyin National High-Tech Industrial Development Zone (JOIND), in Jiangsu Province, China.

By setting up in Jiangyin National High-Tech Industrial Development Zone, the joint venture can benefit from Jiangyin's unique location and mature industrial environment to quickly set up the 12-inch wafer bumping and CP testing production line (Middle-End-Of-Line). Meanwhile, the joint venture can also utilize JCET's nearby advanced back-end packaging production line, which includes Flip-Chip to support advanced Back-End-Of-Line production for 40/45nm, 28nm and below. Together with SMIC's 12-inch front-end advanced chip production line in development, this will be China's first-ever domestic 12-inch advanced IC manufacturing supply chain. This supply chain will shorten the overall manufacturing cycle time. More importantly, its close proximity to China's consumer electronic industry and the world's largest end-market, will allow our customers to respond with a shorter time-to-market window, and therefore better serve the fast changing consumer electronic market.

Dr. Tzu-Yin Chiu, SMIC's Chief Executive Officer and Executive Director commented, "The Yangtze River Delta is regionally the strongest, largest, and most developed ecosystem in China's IC industry. Jiangyin is located in the center of Yangtze River Delta's 'Golden Triangle' comprised of Suzhou, Wuxi and Changzhou, and is only 180km from Shanghai. Furthermore, Jiangyin has good transportation infrastructure and is a hub of human talents. With our strategic partner JCET located in Jiangyin, our joint venture will rely on JCET's existing manufacturing base and established facilities, thus, the mid and back-end lines will be constructed nearby to increase its dominance in the area, shorten its lead-time, and provide a one-stop service for customers. The initiation and implementation of the project will benefit SMIC's ramp up of 28nm mass production and will help increase the capability of China's semiconductor industry."

Mr. Xinchao Wang, Chairman of JCET stated, "SMIC and JCET's joint venture in Jiangyin will combine our companies' strengths and enhance our long-term relationship; furthermore, the joint venture will focus on upgrading the domestic 3D IC industry chain to world-class standards."

Jian Shen, Mayor of Jiangyin and Director of Jiangyin High-Tech Zone said, "SMIC and JCET are the most prominent companies in China's semiconductor industry. The joint venture will help Jiangyin to become an important component of China's most advanced semiconductor ecosystem. The Jiangyin municipal government gives its full support to this project in order to establish Jiangyin as one of the leading integrated circuit manufacturing bases, and to accelerate the growth and development of China's semiconductor industry."

SEMATECH and CNSE/SUNY Launch New Patterning Center

SEMATECH and the newly merged SUNY College of Nanoscale Science and Engineering (CNSE) / SUNY Institute of Technology (SUNYIT) announced they have launched their joint Patterning Center of Excellence. The new Center will leverage the CNSE/SUNYIT lithography infrastructure which includes state-of-the-art film deposition and etch capability, leading-edge patterning systems and SEMATECH’s Resist Materials Development Center’s (RMDC) EUV imaging capabilities.

The Patterning Center of Excellence (CoE) will enable lithography equipment and lithographic materials manufacturing companies access to a vertically integrated semiconductor processing facility. The new Center aims to reduce the tangible and intangible costs of developing critical lithography materials for individual semiconductor companies. CNSE has continued to build capability, enabling technological excellence as represented by the Center for Semiconductor Research (CSR), a leading-edge research center valued at more than $1 billion established at CNSE in May 2005; the Global 450 Consortium (G450C), which is focused on building the 450mm wafer and equipment development environment; and by CNSE’s membership in SEMATECH.

“Building on SEMATECH’s recent achievements in mask blank and resist, the new Patterning Center will provide the critical capabilities that will continue to produce the results that our members and the industry need to show that EUV lithography is manufacturable,” said Michael Lercel Senior Director and Chief Technologist at SEMATECH. “Furthermore, the new Center will provide an excellent platform for advancing cost-effective semiconductor materials and process solutions needed to enable EUV and emerging patterning technologies.”

“The new Patterning Center further builds on the world-class capabilities enabled by the SEMATECH-CNSE/SUNYIT partnership to support the commercialization of EUVL technologies,” said Dr. Michael Liehr, Executive Vice President of Innovation and Technology of the newly merged CNSE/SUNYIT. “New York State continues to chart a pioneering path for the semiconductor industry under the leadership of Governor Andrew Cuomo, and we are delighted to support the advanced technology needs of our global corporate partners and the industry.”

Advances in lithographic patterning critically depend on the timely availability of enabling resists and materials. The new center, a vital component that builds on SEMATECH’s mask blank and novel imaging efforts, will enable companies to assess their materials, test new tooling, and validate designs for the manufacturing EUVL and other next-generation technologies through access to the newly merged CNSE/SUNYIT’s advanced fabrication facilities.

“The challenges for advanced lithography are developing resist processes that meet the stringent resolution, linewidth roughness, and sensitivity specifications,” said Kevin Cummings, SEMATECH’s Director of Lithography. “These processes will not be available in time without intervention, and the Patterning Center is the place where the industry’s the most advanced technologists can come together and partner to commercialize extreme ultraviolet (EUV) lithography and other technologies for the manufacturing of future nanoelectronics devices.”

“The industry is at a crossroads,” said Warren Montgomery, Assistant Vice President of Advanced Technology and Business Development at the newly merged CNSE/SUNYIT. “The high cost of R&D has made it very difficult to do the research and development needed to continue the drive to smaller and smaller features sizes. The creation of collaborative ‘centers’ like the Centers of Excellence at CNSE and this newly created Patterning Center, being created by CNSE and SEMATECH, will enable R&D to continue while keeping the economics reasonable.”

“SEMATECH remains committed to finding cost-effective solutions through its connections with a broad base of member company engineers, suppliers, and academic researchers to ensure the affordable evolution of emerging lithography technologies,” said Edward Barth Director of Strategic Growth Initiatives at SEMATECH. “Building on SEMATECH’s latest development efforts in mask and novel imaging, the new Center will provide an excellent platform for advancing cost-effective semiconductor materials and process solutions for future nanoelectronics devices.”

Over the past decade, SEMATECH has enabled fast cycle time of resist and materials development by providing the industry access to successive generations of small field exposure tools. In addition, SEMATECH’s projects have succeeded in measuring the outgassing characteristics in hundreds of EUV resists and materials formulations, and delivering thousands of EUV exposure shifts to member companies that have enabled tens of thousands of materials formulations to be evaluated.

CNSE/SUNYIT has, over the past decade, enabled advanced 193nm resist and materials development, etch characterization, defect characterization and integrated process flow demonstration to its partner ecosystem.

SEMATECH and CNSE/SUNYIT’s new Patterning Center is taking the collaboration with CNSE/SUNY IT and its global ecosystem and research network one step further by enabling them to share the costs for advancing resist and materials and process development to support the critical needs of industry.

Sony Invests in Stacked Image Sensor Manufacturing

Sony Corp. has revealed it plans to invest about $340 million to boost its production of stacked CMOS image sensors in support of the demand brought about by the requirements for devices that include smartphones and tablets. In January 2014 Sony announced its plans to establish and invest in Yamagata Technology Centre (Yamagata TEC) as a facility mainly conducting the mastering process for stacked CMOS image sensors.

The latest investment is expected to enable Sony to complete subsequent stages of production, including the layering process, at Nagasaki TEC on semiconductor chips that have undergone the mastering process at Yamagata TEC, providing Sony with a fully integrated production system for stacked CMOS image sensors.

The stacked image sensor process makes the back-illuminated pixels on a separate wafer to the circuits used for signal processing. Mastering of this stacked structure refers to the manufacture of the photodiodes and wiring the stacked CMOS image sensors together.

This investment forms part of Sony's mid- to long-term plan to increase its total production capacity for image sensors to about 75,000 wafers per month, and is expected to increase the current capacity of roughly 60,000 wafers per month to nearly 68,000 wafers per month in August 2015.

Sony was the leading supplier of CMOS image sensors in 2012, according to Yole Development. Sony had 21 per cent of the market ahead of 19 per cent and Samsung on 18 per cent.

New Fabless Semiconductor Company by Fujitsu and Panasonic

A new fables company is formed by Japanese leading electronics companies Fujitsu Semiconductor, Panasonic, and also another investor Development Bank of Japan Inc. (DBJ).

The new CEO for the company is Mr. Yasuo Nishiguchi.

Fujitsu Semiconductor also announced its manufacturing facilities in Mie and Aizu-Wakamatsu, Japan to operate as new independent companies by the end of 2014. The new Aizu foundry company will consist of a 150mm fab company and 200mm fab company.

ON Semiconductor is taking a 10% ownership interest in the new Aizu foundry company's 200mm fab company.

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